NXP Semiconductors /LPC43xx /SDMMC /MINTSTS

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Interpret as MINTSTS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CDET)CDET 0 (RE)RE 0 (CDONE)CDONE 0 (DTO)DTO 0 (TXDR)TXDR 0 (RXDR)RXDR 0 (RCRC)RCRC 0 (DCRC)DCRC 0 (RTO)RTO 0 (DRTO)DRTO 0 (HTO)HTO 0 (FRUN)FRUN 0 (HLE)HLE 0 (SBE)SBE 0 (ACD)ACD 0 (EBE)EBE 0 (SDIO_INTERRUPT)SDIO_INTERRUPT 0RESERVED

Description

Masked Interrupt Status Register

Fields

CDET

Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set.

RE

Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set.

CDONE

Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set.

DTO

Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set.

TXDR

Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set.

RXDR

Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set.

RCRC

Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set.

DCRC

Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set.

RTO

Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.

DRTO

Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.

HTO

Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set.

FRUN

FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set.

HLE

Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set.

SBE

Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set.

ACD

Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set.

EBE

End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set.

SDIO_INTERRUPT

Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, this bit is always 0.

RESERVED

Reserved

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